Gallery

 

1. Group Photo

 

 

 

 

 

2. Chip Gallery


(1). MMIC - Power Amplifier 

 

60GHz Power Amplifier with 2D Distributed Power Combining by Metamaterial-based Zero-Phase-Shifter (IMS'12, TMTT'13)

Tapeout Date: Mar 2011

Process: UMC 65nm CMOS 1P6M

With the use of metamaterial based zero-phaseshifter, a new 2D distributed power combining network is developed in this work to simultaneously support distributed amplification and power combining with the minimum implementation expense. Measured results show that the fabricated PA has 8.3dB gain, 7.1% PAE, and 9.7dBm P1dB with 16GHz bandwidth (44 to 60GHz).


A 53-to-73GHz Power Amplifier by 2D Differential Power Combining (RFIC'13)

Tapeout Date: Mar 2012 

Process: GF 65nm CMOS 1P6M

Towards wide bandwidth and high output power density for 60GHz PA design in 65nm CMOS, this project works on a 2D differential power combining network by metamaterial-based zero-phase-shifter. Simultaneous distributed amplification and power combining can be achieved with improved performances in both power density and bandwidth. The PA measurement results show 13.2 dB gain, 8.7% PAE, 13dBm P1dB, and 20GHz bandwidth (53 to 73GHz) within an area of 0.268mm2.


A 54 to 62.8GHz PA with 95.2mW/mm2 Output Power Density by 4x4 Distributed In-phase Power Combining in 65nm CMOS (IMS'14)

Tapeout Date: Mar 2013

Process: GF 65nm CMOS 1P6M

To combine large number of CMOS power transistors within compact area, a 2D distributed in-phase power combiner is proposed with use of metamaterial-based zero-phase-shifter. One 54 to 62.8GHz PA has been demonstrated in 65nm CMOS with a 4×4 distributed power combining of 16 transistors in compact area of 0.48mm2.



(2). MMIC - Voltage Control Oscillator 

60GHz Wide Tuning Range VCO (A-SSCC'12)

Tapeout Date: Jun 2011

Process: STM 65nm CMOS 1P7M

A wide tuning range is required at mm-wave to cover various bands and large PVT variations. This work aims to realize a wide tuning range 60GHz VCO with proposed switch inductor based tuning method.

 

100GHz Voltage Control Oscillator (TCAS-II'13)

Tapeout Date: Jun 2011

Process: STM 65nm CMOS 1P7M

With the exploration of the emerging metamaterial based resonator,people recently find Complementary Split Ring Resonator (CSRR)can exhibit a high quality factor. This work aims to realise a on-chip low phase noise Voltage Control Oscillator with CSRR at 100GHz.

 

77GHz Voltage Control Oscillator (SiRF'13, TMTT'13)

Tapeout Date: Jun 2011

Process: STM 65nm CMOS 1P7M

According to the high quality factor of metamaterial based resonator Split Ring Resonator (SRR), it is possible to realise on-chip low phase noise VCO with SRR. This work presents a VCO approach with SRR at 77GHz.

 

A 75.7GHz to 102GHz Rotary-traveling-wave VCO by Tunable Composite Right /Left Hand T-line (CICC'13)

Tapeout Date: : Mar 2012

Process: GF65nm CMOS 1P6M

With the use of tunable composite-right/left-hand (CRLH) transmission line (T-line), a wide frequency-tuning-range (FTR) mechanism for Mobius-ring rotary-traveling-wave (RTW) VCO is designed in millimeter-wave region. CRLH T-line is implemented in RTW-VCO with inductor-loaded transformer to realize sub-band selection over a wide FTR. Each sub-band is further covered by a varactor for fine-tuning.

 

Wide Frequency-tuning-range CMOS 60GHz VCO by Switching Inductor Loaded Transformer (TCAS-I'14)

Tapeout Date: Jun 2012

Process: GF 65nm CMOS 1P6M

To provide wide frequency tuning range (FTR) with compact implementation area, this work proposes a new inductive tuning method, which is based on a switching inductorloaded transformer by configuring different current return-paths in the secondary coil of the transformer. Different from previous inductive tuning methods, the proposed VCO topology can achieve wide FTR for multiple sub-bands at 60 GHz within compact area by only one transformer. This VCO realizes a low phase noise variation of ±2.5 dB (-105.9 to -110.8 dBc/Hz at 10 MHz offset) in all sub-bands with a FTR of 14.2% from 57.0 GHz to 65.5 GHz. 

 

 A 127-140GHz Injection-locked Signal Source with 3.5mW Peak  Output Power by Zero-phase Coupled Oscillator Network in 65nm CMOS (CICC'14)

Tapeout Date: Oct 2013

Process: GF 65nm CMOS 1P6M

A high output power and high efficiency injection-locked millimeter-wave (mm-wave) signal source is demonstrated by zero-phase coupled oscillator network (CON) at 140GHz. Each oscillator unit-cell is designed by an inter-digital coupler with zero-phase shift and 0.4dB loss at 70GHz, and is further doubled to 140GHz by a push-push frequency doubler. With four in-phase coupled unit-cells, high output power 140GHz signal is generated at the center of the CON by an in-phase power combination of the second harmonics generated by push-push frequency doublers. Moreover, a 9.7% frequency-tuning-range (FTR) centered at 133.5GHz is achieved by inductive tuing at each oscillator unit-cell. The proposed mm-wave signal source is farbicated in 65nm CMOS process with compact core chip area of 0.13mm2. The measured results are: 3.5mW peak output power, 2.4% power efficiency and 26.9mW/mm2 power density. 



(3). MMIC - Receiver 

Ultra-low power CMOS 60GHz Direct-conversion Receiver (RFIT'12, TMTT'13)

Tapeout Date: Dec 2011

Process: UMC 65nm CMOS 1P6M

An 8mW Ultra-low Power 60GHz Direct-conversion Receiver with 55dB Gain and 4.9dB Noise Figure in 65nm CMOS.

A -78dBm Sensitivity 96GHz Super-regenerative Receiver with Quench-controlled Metamaterial Oscillator (RFIC'13)

Tapeout Date: Jun 2012

Process: UMC 65nm CMOS 1P6M

One high-sensitivity CMOS super-regenerative receiver is demonstrated for 96GHz mm-wave imaging based on high-Q metamaterial oscillator. Compared to traditional LC-tank based oscillator, the metamaterial oscillator is developed by a novel folded-differential transmission-line loaded complimentary split-ring resonator (FDTL-CSRR). 

Design of Ultra-low Power 60 GHz Direct-conversion Receivers in 65nm CMOS (TMTT'13)

Tapeout Date: Mar 2012

Process: GF 65nm CMOS 1P8M

An ultra-low-power design of 60-GHz direct-conversion receiver in a 65-nm CMOS process for multi-channel applications under the IEEE 802.15.3c standard. One subthreshold biasing 0.4-V transconductance mixer is designed with a compact quadrature hybrid coupler (160 m 210 m with measured 3-dB intrinsic loss) in receivers to achieve low power of 12.4 mW and high gain of 62-dB. One three-stage low-noise amplifier employs high-Q passive matchings. A high-impedance transmission line is utilized for matching in the multi-channel receiver, respectively. In addition, one new modified Cherry–Hooper amplifier is applied for the variable-gain amplifier design to achieve high gain-bandwidth product and high power efficiency. 

 

A 131.5GHz, -84dBm Sensitivity Super-regenerative Receiver by Zero-phase-shifter Coupled Oscillator Network in 65nm CMOS  (ESSCIRC' 14)

Tapeout Date: Oct 2012

Process: GF 65nm CMOS 1P8M

A CMOS high-sensitivity super-regenerative receiver is proposed for millimeter-wave imaging systems. With quench-control signals, two LC-tank oscillators are coupled in-phase by zero-phase-shifter network in a positive feedback loop. This leads to a high oscillatory amplification and improves the detection sensitivity. The circuit is realized in 65nm CMOS with a core area of 0.06 mm2. Measurements show that the receiver features a sensitivity of −84dBm, a noise-equivalent-power of 0.615fW/Hz0.5, a noise-figure of 7.26 dB and a power consumption of 8.1mW.  

 

A 239-281GHz Sub-Thz Imager with 100MHz Resolution by CMOS Direct-conversion Receiver with on Chip Circular-polarized SIW Antenna(CICC'14)

Tapeout Date: Oct 2012

Process: GF 65nm CMOS 1P8M

A 239-281GHz imager by direct-conversion receiver is demonstrated in 65nm CMOS process with high spectrum resolution and high sensitivity for sub-THz imaging. The sub-THz imager consists of a circular-polarized substrate integrated waveguide (SIW) antenna, down-conversion mixer and power gain amplifier (PGA). The SIW antenna is compact in area of 0.17mm2 with -0.5dB gain and 32.1GHz bandwidth. The single-gate mixer can achieve 80GHz bandwidth centered at 260GHz with a conversion gain of -19dB. High resolution signal detection is achieved by a three-stage PGA with 150MHz bandwidth. The proposed sub-THz imager is fabricated with measurement results: -2dBi conversion gain over 42GHz bandwidth,-54.4dBm sensitivity with 100MHz detection resolution bandwidth, 6.6mW power consumption and 0.99mm2 chip area. Moreover, frequency-dependent sub-THz images are demonstrated as well.



(4). High-speed Analog/RF 


 

A CMOS 60GHz injection-locked frequency divider (IMS'14)

Tapeout Date: Mar 2013

Process: GF 65nm CMOS 

A CMOS 60GHz injection-locked frequency divider (ILFD) is demonstrated in this work by introducing a wide-frequency-range switching-inductor loaded transformer. With different switching conditions, multi-band operation can be realized to improve the locking range with low power consumption and compact area. The 60GHz ILFD together with the entire divider chain has a measured frequency range from 60.8 to 67GHz covered by two switching bands that can be utilized in 60GHz PLL design.

 

 

A 32.5-GS/s Two-Channel Time-Interleaved CMOS Sampler with Switched-Source Follower based Track-and-Hold Amplifier (IMS'14)

Tapeout Date: Mar 2013

Process: GF 65nm RF-CMOS  

This work presents a high speed and low distortion sampler with two-channel time-interleaved sampler with track-and-hold amplifier (THA). The THA is based on switched source-follower with active inductor load such that wide bandwidth in tack-mode and small signal feed-through in hold-mode can be both achieved within compact area. Furthermore, one clock-controlled auxiliary transistor is also introduced to cancel clock feed-through in hold-mode. The measured S-parameters show matched input and output up to 40GHz with 19.3GHz bandwidth in track-mode. The measured spurious-free-dynamic-range (SFDR) is 35dB, and total harmonic distortion (THD) is -30dB sampled at 16.26GS/s in one channel.



 

A 280GHz CMOS On-chip Composite Right/Left Handed Transmission Line based Leaky Wave Antenna with Broadside Radiation (IMS'14)

Tapeout Date: Mar 2013

Process: GF 65nm CMOS 

This work demonstrates a 280GHz leaky wave antenna with broadside radiation by 13-unit-cell periodic composite right/left handed transmission line (CRLH-T-Line) with stacking high-resistivity dielectric layer to enhance antenna radiation efficiency. The design is verified by measurement in THz region from 220 to 325 GHz.



(5). CMOS Image Sensor 


High Speed Super-resolution CMOS Image Sensor (SPIE'12)

Tapeout Date: Apr 2011

Process: GF 0.18μm CMOS 1P6M

The integration of CMOS image sensor and microfluidics becomes a promising technology for bio-medical applications. A high-speed and high-sensitivity CMOS image sensor chip is developed in this project targeted for high-throughput microfluidic imaging system. The image sensor employs the design of column-parallel single-slope analog-to-digital converter (ADC) with digital correlated double sampling (CDS). This initial sensor prototype with timing-control makes it possible to develop high-throughput lensless microfluidic imaging system for different bio-medical applications. The super-resolution image processing is implemented using FPGA off-chip.

High Speed Super-resolution CMOS Image Sensor (BioCAS'12)

Tapeout Date: May 2012

Process: GF 0.18μm CMOS 1P6M 

A high-speed CMOS image sensor chip is developed in this project targeted for high-throughput microfluidic imaging system. The image sensor employs the design of column-parallel single-slope analog-to-digital converter (ADC) with digital correlated double sampling (CDS). The on-chip single-frame super-resolution processing and timing control is implemented for higher resolution and higher sensitivity. This sensor prototype makes it possible to develop high-throughput lensless microfluidic imaging system for different bio-medical applications.

 

CMOS Energy-Harvesting and Imaging (EHI) APS Imager (APCCAS'12)

Tapeout Date: Nov 2011

Process: GF 0.18μm CMOS 1P6M 

A dual-mode CMOS image sensor that can both produce power from light and capture video images on same focal plane is developed. This second version chip is targeted to further reduce the chip power consumption and achieve the self-powered goal.

 

Dual-mode CMOS ISFET ion-image sensor (VLSIC'14)

Tapeout Date: Oct 2012

Process: TSMC 0.18μm CIS 1P6M

A 64×64 CMOS ion-image sensor is demonstrated in this work towards accurate high-throughput DNA sequencing. Dual-mode (pH/image) sensing is performed with ion-sensitive field-effect transistor (ISFET) fabricated in standard CMOS image sensor (CIS) process. After addressing physical locations of DNA slices by optical contact imaging, local pH for one DNA slice can be mapped to its physical address with accurate correlation. Moreover, pixel-to-pixel ISFET threshold voltage mismatch is reduced by correlated double sampling (CDS) readout. Measurements show a sensitivity of 103.8mV/pH and fixed-pattern-noise (FPN) reduction from 4% to 0.3% with speed of 1200fps.

 

A High-sensitivity 135GHz Millimeter-wave Imager by Differential Transmission-line Loaded Split-ring-resonator in 65nm CMOS (ESSDERC'14

Tapeout Date: Oct 2012

Process: GF 65nm CMOS 

A high-sensitivity 135GHz millimeter-wave (mmwave) imager is demonstrated in 65nm CMOS by on-chip meta material resonator: a differential transmission-line (T-line) loaded with split-ring-resonator (DTL-SRR). Due to sharp stop-band introduced by metamaterial load, high-Q oscillatory amplification can be achieved with high sensitivity when utilizing DTL-SRR as quench-controlled oscillator to provide regenerative detection. The developed mm-wave imager pixel has a compact core chip area of 0.0085mm2 with measured power consumption of 6.2mW, sensitivity of -76.8dBm, noise figure of 9.7dB, and noise equivalent power of 0.9fW/pHz with demonstrated mm-wave images.


(6). Other Sensors 



3D CMOS-MEMS Stacking with TSV-less and Face-to-Face Direct Metal Bonding for high sensitivity accelerometer system. (3D-IC'12, VLSIT'14)

CMOS readout circuit is stacked on MEMS accelerometer using face-to-face (F2F) direct metal bonding. F2F bonding provides smaller form factor, latency, and power consumption. The CMOS chip acts as an active cap that encapsulates and provides interconnect routing to the MEMS chip. Metal bonding (Al-Au) was achieved at 300°C/10min/50N. The bond quality meets the requirements during shear and helium leak tests. The stacked CMOS/MEMS chip is verified to be functional and sustains shock test of 500g.



A High-frequency Transimpedance Amplifier for CMOS Integrated 2D CMUT Array towards 3D Ultrasound Imaging (EMBC'13)

Tapeout Date: Jul 2011

Process: GF 0.18μm 30V HV Bipolar/CMOS/DMOS (BCD)

In this project, one transimpedance amplifier based CMOS analog front-end (AFE) receiver is integrated with capacitive micromachined ultrasound transducers (CMUTs) towards high frequency 3D ultrasound imaging. Considering device specifications from CMUTs, the TIA is designed to amplify received signals from 17.5MHz to 52.5MHz with center frequency at 35MHz; and is fabricated in Global Foundry 0.18-μm 30-V high-voltage (HV) Bipolar/CMOS/DMOS (BCD) process. The measurement results show that the TIA with power-supply 6V can reach transimpedance gain of 61dBΩ and operating frequency from 17.5MHz to 100MHz. The measured input referred noise is 27.5pA/√Hz. Acoustic pulse-echo testing is conducted to demonstrate the receiving functionality of the designed 3D ultrasound imaging system.


A High-density Electrical-Impedance Spectroscopy (EIS) Biosensor (Sens Actuators B Chem'12 & '13)

Tapeout Date: Jun 2012

Process: GF 0.18μm 1P6M

A high-density electrical-impedance spectroscopy (EIS) biosensor array has been developed for high throughput and automated counting of specific breast tumor MCF-7 cells. The biosensor array (96×96) consists of densely packed electrodes. Each of the square electrodes has an edge-length of 22μm to capture single MCF-7 cell. The electrodes are electrically addressable by decoding circuit built underneath by 0.18μm CMOS process. EIS spectra of electrodes were recorded over a wide frequency range with and without the presence of cell. Data were numerically fitted with the equivalent circuit model to extract important sensing parameters including cell impedance, electrode impedance, sealing resistance and spreading resistance.




 
3. System Gallery
 
Energy harvesting and clean energy are important society concerns for the future sustainable development. There is negligence that energy could be wasted by individual from homes or buildings. Collaborated with ERI@N, we target to develop an energy cloud system (ECS) that enables smart homes and buildings with the synergy between information technology and energy technology. This project aims to build energy cloud system to monitor and predict of energy profile for residential houses at NTU. Based on the energy sensory hardware developed at NTU, we have developed demand response and dispatch based energy management system in this project. It is important for energy generation perspective as the production of electricity needs to match the consumption and also keep the voltage and frequency stable to avoid damage of the expensive infrastructure. At the same time, consumers should be more willing to accept day-ahead pricing strategy so that they can have enough time is ready to react. In this project, we have integrated energy management algorithm (implemented in Android) into the energy sensory hardware to schedule workloads and reduce the peak consumption with following considerations:
  • Study the day and night residential energy consumption behaviour;
  • Research on the workload characteristics of heating, lighting, cooling and air-conditioning;
  • Develop demand response and dispatch algorithm in NTU energy cloud system.
The immediate application is to deploy our ECS to smart homes, which is capable of monitoring real time energy utilization in a home displayed by user friendly GUI on Android tablets. The smart sockets are installed for power hungry appliances like Air Conditioners and heaters. The smart sockets communicate wirelessly using Zigbee to a smart gateway, where the utilization data is stored in a database for future reference and management. In addition, the smart sensors monitor ambient light, temperature, humidity and user occupancy. For more information about our smart energy cloud system, please visit http://www.ntucmosetgp.net/gallery/energy. Please click for our system demo video on youtube or video on youku.
 


(2). Lensless Microfluidic Imaging System 
 
 
click for our initial demo video on youtube or video on youku


The integration of CMOS image sensor and microfluidic channel has become a promising approach for portable biomedical imaging diagnosis. Different from the traditional microscope imaging systems which usually require intermediary bulky optical lens to constrain the size, weight, and cost, a lensless microfluidic imaging system directly integrates the microfluidic device on the top of CMOS image sensor, as such the image for the sample of interest in microfluidic channels can be directly acquired by projecting light through the sample or by capturing light emitted. By getting rid of optical lens and integrating with CMOS image sensor and system design, one can develop compact and automated biomedical imaging systems for a variety of applications such as cell monitoring, counting, sorting, point-of-care diagnosis. In this project, we are building one such lensless imaging system. Super-resolution image processing is integrated to improve the system resolution. It is used in a system-level model study. Meanwhile, more biomedical applications for this system will be explored. 
The initial video for our system demo can be found in the links above. The 20um-diameter microspheres are flowing in microfluidic channel of 100um-width. The microspheres can be detected and tracked by our lensless imaging system. 

 
 
4. Tool Gallery
 

(1). NVMspice

 

NVM or non-volatile storage is computer memory that can retain the stored information even when not powered. Emerging NVM devices like memristor, spin-transfer torque magnetic tunneling junction (STT-MTJ), phase-change memory draw great interests both from academia and industry. However, one major challenge when designing hybrid CMOS-NVM integrated circuit is the lack of SPICE-like simulator for design validation. Current approach is to describe NVM devices with their equivalent circuits, which is however extremely time-consuming for large scale design simulation due to additional modeling components. Hence NVMspice is introduced based on our recent new modified nodal analysis (MNA) framework, which can effectively support the non-conventional state variables. As such, NVM devices can be stamped into state matrix similarly as one BSIM MOSFET. Compared with equivalent circuit simulation approach, our new MNA based approach exhibits 40x less simulation time for a 32x32 memristor crossbar circuit. For more infomation and tool download, please visit http://www.nvmspice.com/ or click the down load link hereThe demo video for both read and write circuit of STT-MTJ with circuit diagram and netlist is shown here. 

 

(2). 3D-ACME

 

3D-ACME (http://www.3dacme.allalla.com) stands for 3D-IC thermal simulator with modelling of Anisotropic TSV Conductance and Microchannel Entrance effects. It is a software that simulates the steady state temperature of heatsink or microfluidic cooled 3DICs given power consumption, cooling setting and physical set-ups of 3D circuit stacks. Accuracy of this thermal model has been verified against commercial multiphysics solver COMSOL (http://www.comsol.com/). Please click here to download.


(3). 2.5D/3D System Integration Platform

 

The memory-logic-integration design platform is developed with system evaluation for both 2.5D through-silicon-interposer (TSI) and 3D through-silicon-via (TSV) based integrations. The platform is running under Linux environment and users can configure the floorplan as either 2.5D integration by TSI I/Os or 3D by TSV I/Os as well as layer number, core number and I/O position. In this platform, firstly the cycle-accurate simulator is used to perform functional simulation. The core simulation is performed by gem5 and memory simulation is performed by DrSim. The benchmarks are from several sources, including SPEC 2006, PARSEC and Phoenix. Secondly the output information from simulator are translated by link scripts for physical analysis. The core power analysis is done by McPAT and the memory power analysis is done by CACTI. For I/O power, we use our own developed models for both 3D RC-interconnected TSV I/Os and 2.5D transmission-line-interconnected TSI I/Os. All these power results are then fed into a thermal simulator 3D-ACME for thermal runaway failure study. Click here to download the whole platform package.